This invention relates to a thin film transistor and a method for the manufacture thereof and, more particularly, to a method which can be easily performed with a reduced number of process steps, which can give a high yield and wherein a thin film transistor array manufactured by a self alignment process is highly reliable and capable of exhibiting good characteristics.
An example of a prior art method for making a thin film transistor is shown in FIG. 1 of the accompanying drawings which illustrates the prior art thin film transistor in cross-sectional view. As shown in FIG. 1, the prior art thin film transistor is of a construction comprising an insulating substrate 1, made of glass or the like and having one surface formed with a control gate electrode 2 thereon, an insulating film 3 covering the control gate electrode 2, a semiconductor layer 4 overlaying the insulating film 3, and source electrode 5 and the drain electrode 6 successively formed thereon. The gate electrode 2 is formed by the use of a masked vapor deposition of a metal such as Al, Au, Ta, Ni or the like whereas the insulating film 3 is made of Al.sub.2 O.sub.3, SiO, SiO.sub.2, CaF.sub.2, Si.sub.3 N.sub.4 or the like and formed by the use of a vacuum deposition technique, a sputtering technique, a chemical vapor deposition technique or the like. Where the gate electrode 2 is made of Al, Ta or the like, it is possible to form the insulating film 3 by the use of an anodization technique. On the other hand, the semiconductor layer 4 is generally made of CdSe, CdS, Te or the like and is formed by the use of a vacuum deposition technique, a sputtering technique or the like. Each of the source and drain electrodes 5 and 6 is made of a material, for example, Au, Ni, In or the like, which is capable of exhibiting an ohmic contact with the semiconductor layer 4.
Other than the thin film transistor of the construction shown in FIG. 1, conventionally available are a thin film transistor wherein, as shown in FIG. 2, the semiconductor layer 4 and a combination of the source and drain electrodes 5 and 6 are substantially reversed in position with respect to that shown in FIG. 1, a thin film transistor wherein, as shown in FIG. 3, the semiconductor layer 4 is formed on the substrate 1 together with and between the source and drain electrodes 5 and 6 on the substrate 1 and the gate electrode 2 is deposited on the layer 4 with the insulating layer 3 formed between the electrode 2 and the layer 4, and a thin film transistor wherein, as shown in FIG. 4, respective portions of the source and drain electrodes 5 and 6 contact the semiconductor layer 4 is a substantially reversed manner with respect to that shown in FIG. 3.
When it comes to the fabrication of an integrated circuit by the use of any of these prior art thin film transistors, or when it comes to the use of any of these prior art thin film transistors as an addressing element for a matrix type liquid crystal display device, pattern dimensions of the source, drain and gate electrodes and the semiconductor layer are required to be of a precision smaller than several microns. In addition, since the relative positioning of these electrodes is required to a comparable or higher precision, the method requires a high level technology with an increased number of process steps. Moreover, in any of the thin film transistors manufactured according to conventional methods, an overlapping area tends to be formed between the gate and source electrodes, involving generation of an unnecessary capacitance therebetween, on the one hand, and rendering a portion of the insulating film at the overlapping area to be susceptible to dielectric breakdown, on the other hand. Therefore, the insulating film in the prior art thin film transistor is susceptible to damage.